RISC-V

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RISC-V (pronounced "risk-five") is a license-free, modular, extensible instruction set architecture (ISA).

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RISC-V With Linux 6.15 Adds Support For BFloat16 "BF16" Instructions [and more] (www.phoronix.com)

submitted 1 week ago by [email protected] to c/[email protected]

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Merged on Friday for the nearly-over Linux 6.15 merge window were the RISC-V CPU architecture updates for this next kernel release.

RISC-V with Linux 6.15 brings build improvements thanks to a re-architecting of the Kconfig build system options around RISC-V for selecting sub-architecture features.

For the Linux 6.15 kernel with RISC-V there is also support for building relocatable non-MMU kernels, support for huge PFNMAPS to improve TLB utilization, support for runtime constants, new RISC-V instructions supported, and a variety of fixes.

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[–] [email protected] 2 points 1 week ago (1 children)

Why does the os care about some new arithmetic instructions being present? Are there new registers to save or what?

[–] [email protected] 3 points 1 week ago

I would guess these are for device-tree specifications and run-time detection of what extensions some RISC-V CPU supports. Also might be some support for using these extensions in some common kernel code that is used by other parts of the kernel. But to be sure we would need to check the commits themselves.