RISC-V

direct Youtube link: https://youtube.com/watch?v=4TmHSsIU1ns

cross-posted from: https://lemmy.world/post/24756689

Hello all,

I've only done very basic research on RISC-V as the DeepCompute RISC-V mobo caught my attention. For the software side, I know that support will (probably) come with time, so I can't really do much besides lament over it huh?

The main thing that caught my eye is that the DeepCompute mobo seems to only accept SD cards for storage. Is this a hard limit of RISC-V or is it just a limit of current technology (i.e. we need time to build something over RISC-V like x86_64/amd64?)?

I've also heard that Linux ran vaguely slow on RISC-V architectures, but ive only heard it as a passing comment. How true is this? Would future developments/putting in more time like for the decades behind x86_64 developments alleviate the speed issue?

Thank you all!

Finally my 6€ come back 😓 Source: https://x.com/milkv_official/status/1879799138705195303

You might get intimidated when you hear OS or kernel development, the basic functions of an OS (especially the kernel) are surprisingly simple. Even Linux, which is often cited as a huge open-source software, was only 8,413 lines in version 0.01. Today's Linux kernel is overwhelmingly large, but it started with a tiny codebase, just like your hobby project.

We'll implement basic context switching, paging, user mode, a command-line shell, a disk device driver, and file read/write operations in C. Sounds like a lot, however, it's only 1,000 lines of code!

[…]

In this book, I chose RISC-V as the target CPU because:

• The specification is simple and suitable for beginners.
• It's a trending ISA (Instruction Set Architecture) in recent years, along with x86 and Arm.
• The design decisions are well-documented throughout the spec and they are fun to read.

We will write an OS for 32-bit RISC-V. Of course you can write for 64-bit RISC-V with only a few changes. However, the wider bit width makes it slightly more complex, and the longer addresses can be tedious to read.

A team from China’s top government research academy pledged to produce this year a processor based on the open-source chip-design architecture RISC-V, as Beijing advances its semiconductor self-reliance drive amid escalating US restrictions.

The Chinese Academy of Sciences (CAS) will be able to deliver its XiangShan open-source central processing unit in 2025, wrote Bao Yungang, deputy director at the academy’s Institute of Computing Technology, in a Weibo post on Sunday.

cross-posted from: https://lemmy.bestiver.se/post/174306

Comments

cross-posted from: https://lemmy.world/post/23802973

Can it topple x86 and Arm, or is the gap too wide to close?

Finally! After weeks of work, I have successfully booted postmarketOS on both of those devices. This should hopefully make the adoption of both, RISC-V and PostmarketOS easier.

The goal of this text is to provide an overview of RISC-V Vector extension (RVV), and compare — when applicable — with widespread SIMD vector instruction sets: SSE, AVX, AVX-512, ARM Neon and SVE.

The RISC-V architecture defines four basic modes (32-bit, 32-bit for embedded systems, 64-bit, 128-bit) and several extensions. For instance, the support for single precision floating-point numbers is added by the F extension.

The vector extension is quite a huge addition. It adds 302 instructions plus four highly configurable load & store operations. The RVV instructions can be split into three groups:

• related to masks,
• integer operations,
• and floating-point operations.

When a CPU does not support floating-point instructions, it still may provide the integer subset.

RVV introduces 32 vector registers v0, ..., v31, a concept of mask (similar to AVX-512), and nine control registers.

Unlike other SIMD ISAs, RVV does not explicitly define size of vector register. It is an implementation parameter (called VLEN): the size has to be a power of two, but not greater than 216 bits. Likewise, the maximum vector element size is an implementation parameter (called ELEN, also a power of two and not less than 8 bits). For example, a 32-bit CPU might not support vectors of 64-bit values.

But generally, we may expect that a decent 64-bit CPU would support elements having 8, 16, 32 or 64-bit, interpreted as integers or floats.

Hi there! I'm still trying to build alternative OSs on the DC-ROMA PAD II and I have successfully built spacemit's u-boot but the board used in the ROMA PAD does not seem to be supported. I asked deepcomputing about it but since people might already have that config somewhere I thought I'd ask.

It looks like the upcoming Linux 6.13 cycle will be adding RISC-V support for user-space pointer masking and tagged address ABI. RISC-V pointer masking can be used for implementing memory tagging akin to the Arm Memory Tagging Extension (MTE) by way of ignoring various bits of the effective address on RISC-V platforms. Memory tagging can help with the memory safety state of user-space applications.

Spacemit advertises their K1 soc as compliant with the RVA22 but this table suggests it might not be: https://mastodon.giftedmc.com/@haui/113372897786006093

What am I missing?

Hi folks! I got my order of the now out of stock RISCV tablet DC-ROMA PAD II today.

Hardware It is decently manufactured, about 11 inches in size, has wifi, a small keyboard (ordered on top), headphone jack, 8 cores spacemit cpu, usbc connector and sd card slot (and maybe sim but unsure).

Operating System The device comes with ubuntu 24.04 on the internal storage and a micro sd card with debian. Both run decent oob but what comes next is rather peculiar

What happened so far The devices run patched everything as far as I can see. upgrading ubuntu bricked gnome shell so that it permanently maxxes out one core and makes the device unusable. Maybe I should have made a backup first but I didnt think it would go unusable asap. Pretty much the same happened to the debian system, which I did backup before updating. The real issue is that there are barely any riscv images out there and building them is quite the endeavor.

So for now I'll use the backup of the debian system until I have familiarized myself with the hardware enough to know what I can and cant do.

Fair warning To those thinking of purchasing this device, be careful. It is marketed as a developer device and even as a dev, it is very rough to use at this point. there is an online manual with 7 pages which explains how to turn the device on, thats it. no info about debugging tools AT ALL. You have been warned.

Future Of course I'm not done with it and will attempt to port postmarketOS to it as well as learn how to make reproducible images for other OSs. Let me know if you have any questions. Feel free to give advice if you are experienced. This is my first riscv device.

cross-posted from: https://lemmy.zip/post/25094802

Nvidia quietly adopts RISC-V and replaces proprietary microcontrollers.

cross-posted from: https://lemmy.ml/post/21673583

RISC-V International, the global standards organization, today announced that the RVA23 Profile is now ratified. RVA Profiles align implementations of RISC-V 64-bit application processors that will run rich operating systems (OS) stacks from standard binary OS distributions. RVA Profiles are essential to software portability across many hardware implementations and help to avoid vendor lock-in. The newly ratified RVA23 Profile is a major release for the RISC-V software ecosystem and will help accelerate widespread implementation among toolchains and operating systems.

Each Profile specifies which ISA features are mandatory or optional, providing a common target for software developers. Mandatory extensions can be assumed to be present, and optional extensions can be discovered at runtime and leveraged by optimized middleware, libraries, and applications.

Key Components of RVA23 Include:

• Vector Extension: The Vector extension accelerates math-intensive workloads, including AI/ML, cryptography, and compression / decompression. Vector extensions yield better performance in mobile and computing applications with RVA23 as the baseline requirement for the Android RISC-V ABI.
• Hypervisor Extension: The Hypervisor extension will enable virtualization for enterprise workloads in both on-premises server and cloud computing applications. This will accelerate the development of RISC-V-based enterprise hardware, operating systems, and software workloads. The Hypervisor extension will also provide better security for mobile applications by separating secure and non-secure components.