sith

Yeah, I'm only interested in the "least bad" here. Taking usability, libre and performance into account. I don't think that even the Framework Laptop 13 RISC-V will be completely libre.

Thanks for input though!

Actually, it is not true from what I've learned. For example, Intel is about to push chipset/bios upgrades to boost the performance of the new Core Ultra 9 285k. And that kind of driver can at best be open source and in the upstream kernel or at worst closed source and only installed by some windows only bloatware.

Nice website! Thanks!

Having to use windows when upgrading firmware is very Linux unfriendly.

Ditching the Linux kernel is probably a good idea. Or at least run your own fork. Which I expect that many state actors and large companies already do. Also, I suspect that we'll see more large public kernel forks sooner rather than later. Even sooner if Linus retires.

To be honest, I don't care that much for myself. Guess I wasn't completely honest in OP. I'm just a nobody who gladly exposes his soft parts in exchange for cheap and easy access cat videos and general dopamine. Rather I'm thinking about what strategies policy makers, companies, NGOs and the general public should consider, as we crash into even more exciting times.

Ah, I think I have a better understanding of the PCIe hardware protocol now. Feel a bit more confident regard a 2 x8 setup. Thanks.

Just for the record: my understanding is that the HW protocol performs a handshake which settles the number of lanes that will be used when establishing a link. And the PCIe standard is always backwards compatible, so things should work just fine even if I buy something that says PCIe 6.0 later. Or at least the lower layers of the protocol should be compatible. And as long bandwidth isn't an issue.

Your contribution was noise. Not an answer. Do better next time.

Maybe I should rephrase my question.

Are PCIe 5.0 or backwards compatible 6.0+ devices (GPUs), that say x16 (16 lanes) in their product specification, required by the PCIe standard to also support only 8 lanes? I.e. can the device transceiver decide to not connect if not all lanes are available at the protocol level? I'm not referring to slot size here.

The thing is that there are motherboards that have 2 PCIe 5.0 16x slots that are connected to the CPU (hopefully not false marketing). But the slots are downgraded to 8x if you connect two devices, since a AM5 CPUs only have 24 lanes.

I probably need to read the PCIe 5.0 standard document if I want to be sure.

Because of admiralty law.

I did Google and I didn't find an answer.

Also, you might grow a little bit as a human by reading this thread : https://lemmy.zip/post/27991591

Happy holidays!

I did Google and I didn't find an answer.

Also, you might grow a little bit as a human by reading this thread : https://lemmy.zip/post/27991591

Happy holidays!