RISC-V

Has anyone used such a system as a "daily driver"?

What do you need to do in order to boot a normal distro such as Debian or such? How does it stand from the perspective of user/software freedom? What sorts of proprietary sh#ts does it need to be usable? What sorts of compromises that may not be obvious at first glance?

Also how does it "feel" day to day?

The SG2044 is the successor of the SG2042, with the same 64 core count but 8 LPDDR5X channels, 80 PCIe gen 5 lanes, and improved clock speed.

From what I can find in articles and reddit it supposed to have a launch date of 2024, but its not available on the sophon website or any other.

I am starting to worry it has been silently canceled, so does anyone know what happend to it? And if it's still coming what the projected release date is now?

Merged on Friday for the nearly-over Linux 6.15 merge window were the RISC-V CPU architecture updates for this next kernel release.

RISC-V with Linux 6.15 brings build improvements thanks to a re-architecting of the Kconfig build system options around RISC-V for selecting sub-architecture features.

For the Linux 6.15 kernel with RISC-V there is also support for building relocatable non-MMU kernels, support for huge PFNMAPS to improve TLB utilization, support for runtime constants, new RISC-V instructions supported, and a variety of fixes.

cross-posted from: https://lemmy.zip/post/35528933

China is doubling down on the RISC-V architecture.

cross-posted from: https://lemmy.ml/post/28025426

The European Chips Act has set ambitious goals and its implementation is a significant pan-european effort. From an academic perspective, last year we published an open letter emphasizing the critical importance of open-source EDA for academia in Europe. We were excited and grateful to see that this initiative triggered the definition of a European roadmap in this area, and a matching Chips JU call for project funding. We believe that the projects funded by this call will have a significant impact. Moreover, we already see rising interest from many EU stakeholders, with increasing investments into open-source chip design, especially in open source IP development (e.g. RISC-V cores), and open source EDA tools.

One additional critical barrier remains toward the end-goal of building real open-source chips, especially for prototyping and education: namely, streamlining the access to open source chip production facilities (foundries) is essential. Programs like ChipIgnite, Tiny Tapeout and IHP’s open source program have become “guiding stars” that demonstrate that everyone with a computer can build chips. We believe that having low-cost, regular and easy access to chip production is critical to create excitement and build up expertise, widening the pool of chip designers with tape-out experience: a true silicon democratization and a further de-mystification of chip design.

The CPU seems similar to the spacemit k1, but apparently there is no information about it. Too cheapt for rvv extensions?

In Europe 8GB version for less than 60€

cross-posted from: https://lemmy.world/post/26398664

cross-posted from: https://lemmy.world/post/25906238

cross-posted from: https://lemmy.ml/post/25900262

An educational implementation of a parallel processor in system-verilog.

The Intro to GPU Architecture chapter is a short write-up on the theoretical basics needed to understand the GPU implemented in this repository.

We’re happy to share that DeepComputing’s DC-ROMA RISC-V Mainboard for Framework Laptop 13 is now in stock and shipping in the Framework Marketplace. This is very much a developer-focused board to help accelerate maturing the software ecosystem around RISC-V, so we recommend waiting for future RISC-V products if you’re looking for a consumer-ready experience. We shared more detail on the Mainboard in an earlier blog post and video, but as a quick summary, this is powered by a StarFive JH7110 processor that uses the open source RISC-V ISA. The team at DeepComputing designed it to drop directly into a Framework Laptop 13 chassis or Cooler Master Mainboard Case.

T-HEAD is a wholly owned subsidiary of Alibaba, one of China's largest tech companies. Over the past few years, T-HEAD has created a line of RISC-V cores. Alibaba seems to have two motivations for pushing RISC-V. On one hand, the company stands to benefit from creating cost effective chips optimized for areas it cares about, like IoT endpoints and edge computing. On the other, Alibaba almost certainly wants to reduce its dependence on foreign imports. RISC-V is an open instruction set, and isn't controlled by US or British corporations like x86-64 or ARM. T-HEAD's RISC-V push can thus be seen more broadly as a part of China's push to create viable domestic microchips.

Xuantie C910 slots into the "high performance" category within T-HEAD's lineup. Besides joining a small number of out-of-order RISC-V cores that have made it into hardware, C910 is an early adopter for RISC-V's vector extension. It supports RVV 0.7.1, which features masking and variable vector length support. T-HEAD has since released the C920 core, which brings RVV support up to version 1.0, but otherwise leaves C910 unchanged. From Alibaba's paper, with descriptions added in red by Clam. PIU and PLIC appear in the dual core diagram below.

C910 targets "AI, Edge servers, Industrial control, [and] ADAS" as possible applications. It's also T-HEAD's first generation out-of-order design, so taking on all those applications is ambitious. C910 is implemented in clusters of up to four cores, each with a shared L2 cache. T-HEAD targets 2 to 2.5 GHz on TSMC's 12nm FinFET process, where a C910 core occupies 0.8 mm2. Core voltage is 0.8V at 2 GHz, and 1.0V at 2.5 GHz. On TSMC's 7nm process, T-HEAD managed to push core frequency to 2.8 GHz. T-HEAD's paper further claims dynamic power is around 100 microwatts/MHz, which works out to 0.2W at 2 GHz. Of course, this figure doesn't include static power or power draw outside the core. Yet all of these characteristics together make clear C910 is a low power, low area design.

This article will examine C910 in the T-HEAD TH1520, using the LicheePi single board computer. TH1520 is fabricated on TSMC’s 12nm FinFET process, and has a quad-core C910 cluster with 1 MB of L2 running at 1.85 GHz. It’s connected to 8 GB of LPDDR4X-3733. C910 has been open-sourced, so I’ll be attempting to dig deeper into core details by reading some of the source code – but with some disclaimers. I’m a software engineer, not a hardware engineer. Also, some of the code is likely auto-generated from another undisclosed source, so reading that code has been a time consuming and painful experience. Expect some mistakes along the way.

The Devroom will be held on February 1 (Saturday), 2025 in Brussels, Belgium. Topics related to RISC-V encompasses the RISC-V ISA, open source RISC-V hardware (e.g. cores, SoCs, accelerators), and open source RISC-V software (e.g. OS ports, emulators, toolchains).

The default duration for talks is 45 minutes including discussion. Presentations will be recorded and streamed.

RISC-V has seen a flurry of activity over the past few years. Most RISC-V implementations have been small in-order cores. Western Digital’s SweRV and Nvidia’s RV-RISCV are good examples. But cores like those are meant for small microcontrollers, and the average consumer won’t care which core a company selects for a GPU or SSD’s microcontrollers. Flagship cores from AMD, Arm, Intel, and Qualcomm are more visible in our daily lives, and use large out-of-order execution engines to deliver high performance.

Out-of-order execution involves substantial complexity, which makes SiFive’s Performance P550 and T-HEAD’s Xuantie C910 interesting. Both feature out-of-order execution, though a quick look at headline specifications shows neither core can take on the best from AMD, Arm, Intel, or Qualcomm.

To check on RISC-V’s progress as its cores move toward higher performance targets, I’m comparing with Arm’s Cortex A73 and Intel’s Goldmont Plus. Both have comparably sized out-of-order execution engines.

Geekbench 6.4 introduces support for RISC-V Vector Extensions, boosting the performance of workloads that leverage SIMD instructions when run on RISC-V CPUs that implement RVV.

RISC-V is a relatively young and open source instruction set. So far, it has gained traction in microcontrollers and academic applications. For example, Nvidia replaced the Falcon microcontrollers found in their GPUs with RISC-V based ones. Numerous university projects have used RISC-V as well, like Berkeley’s BOOM. However, moving RISC-V into more consumer-visible, higher performance applications will be an arduous process. SiFive plays a key role in pushing RISC-V CPUs toward higher performance targets, and occupies a position analogous to that of Arm (the company). Arm and SiFive both design and license out IP blocks. The task of creating a complete chip is left to implementers.

By designing CPU blocks, both SiFive and Arm can lower the cost of entry to building higher performance designs in their respective ISA ecosystems. To make that happen within the RISC-V ecosystem though, SiFive needs to develop strong CPU cores. Here, I’ll take a look at SiFive’s P550. This core aims for “30% higher performance in less than half the area of a comparable Arm Cortex A75.”

Just as with Arm’s cores, P550’s performance will depend heavily on how it’s implemented. For this article, I’m testing the P550 as implemented in the Eswin EC7700X SoC. This SoC has a 1.4 GHz, quad core P550 cluster with 4 MB of shared cache. The EIC7700X is manufactured on TSMC’s 12nm FFC process. The SiFive Premier P550 Dev Board that hosts the SoC has 16 GB of LPDDR5-6400 memory. For context, I’ve gathered some comparison data from the Qualcomm Snapdragon 670 in a Pixel 3a. The Snapdragon 670 has a dual core Arm Cortex A75 cluster running at 2 GHz.